Design Automation for Differential MOS Current-Mode Logic Circuits by Stéphane Badel & Can Baltaci & Alessandro Cevrero & Yusuf Leblebici

Author:Stéphane Badel & Can Baltaci & Alessandro Cevrero & Yusuf Leblebici
Language: eng
Format: epub
ISBN: 9783319913070
Publisher: Springer International Publishing

4.2.2 Analysis of BDDs and MCML Networks

The analysis of a BDD is the task of extracting information from a given structure. The extracted information can be related to the logic function performed by the BDD and its properties, and in the present context, it can pertain to properties of the equivalent MCML network.

Given a BDD, as we have seen, one can evaluate the result of the logic function for a given set of input values by tracing the path corresponding to the set of input variable values, starting from the root and ending at either one of the leaf nodes. Therefore, each path in the BDD starting from the root and ending at the leaf defines an implicant of the function—that is, a product term implying a true value of the function. Thus, by tracing all paths starting from the root and ending at the leaf, it is possible to find all implicants, defining the on-set of the function; the function can then be written as the sum of these implicants. Conversely, writing the sum of cubes corresponding to paths ending at the results in an expression of the complemented function.

As an example, considering the BDD of Fig. 4.5a, there are two paths from the root to the node: and . The function is thus . Conversely, there is a single path to the node, which is A → B →, and the inverted function can be written as .

Regarding the properties of the corresponding MCML network, as we have seen, each node corresponds physically to a differential pair. The number of levels of the network, i.e. the number of stacked differential pairs, is given by the length of the longest path. As it was seen in Chap. 2, this number has a strong influence on the performance of the gate: the higher the number of levels, the larger all transistors must be sized to preserve the noise margin, therefore the larger the speed and area penalties. Also, for a given node in the network, its position is given by the longest path starting from this node. As it was seen, the delay from a given input to output increases for inputs located at lower levels in the network, due to the increased parasitics between the input and the output. In the BDD of Fig. 4.5, the A input is at level 2, since the longest path goes through B and two edges, and the B input is at level 1.

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